verified connector library

Liebert/Vertiv UPS (IntelliSlot Modbus)

Register map(s) for this device, each at the trust rung it earned. Addresses are 0-based as on the wire; word order and scaling are only confirmed at the hardware-verified rung.

interop-verified

Read + decoded cleanly over a real network vs an independent third-party Modbus test server (transport and framing; reads are remapped into the server's register window, so the map's own addresses are NOT exercised). Does NOT prove word order/scaling against the actual device.

pointaddress (0-based)typescaleunit
voltage_in_x_y0U161
voltage_in_y_z1U161
voltage_in_z_x2U161
voltage_out_a_b3U161
voltage_out_b_c4U161
voltage_out_c_a5U161
voltage_out_a_n6U161
voltage_out_b_n7U161
voltage_out_c_n8U161
current_out_a9U161
current_out_b10U161
current_out_c11U161
ground_current12U160.1
neutral_current13U161
kva14U161
kw15U161
frequency16U160.1
percent_capacity_a17U161
percent_capacity_b18U161%
percent_capacity_c19U161deg C
power_factor20U160.01deg C

link settings as documented (unverified): RTU; baud 9600/19200/38400; FC 01,02,03,04,05,06,15,16; Supports EIA-485/422 2 wire physical port.

bench facts as documented (unverified)
terminals2 wire
connectorEIA-485/422
wiring notesSupports EIA-485/422 2 wire physical port.
max registers/read127
protocol notesWrite Multiple Registers supports writing values into a block of contiguous registers (1 to 120).
doc revisionSL-28170_REV11_03-14
field reports — community-sourced, unverified (checked 2026-06-11)
  • Users attempting to read registers on specific models (e.g., Liebert GXT5) may encounter IllegalAddress errors if they attempt to read holding registers (FC 03) instead of input registers (FC 04) as specified in the manual. [source]
  • On some Liebert GXT MTX+ models, users report being unable to read discrete input status bits (starting at 10002 / 10042) using standard Modbus scanners, while holding registers are accessible. [source]
  • Frequency and Power Factor registers require scaling (divided by 10 and 100 respectively) to obtain the actual values, which can cause integration confusion if not handled in the client. [source]
  • confirmed: comms defaults (baud rates 9600/19200/38400, RTU framing, parity N, stop bits 1, EIA-485/422 2-wire physical port) — confirmed by Table 2.1 of SL-28170 [12.1.2]
  • confirmed: function codes [1, 2, 3, 4, 5, 6, 15, 16] — confirmed by Table 2.2 of SL-28170
  • confirmed: quirks (max_read_registers: 127, Write Multiple Registers supports writing values into a block of contiguous registers 1 to 120) — confirmed by Section 2.3 of SL-28170
  • confirmed: register map summary (voltage_in_x_y @ 0, voltage_in_y_z @ 1, etc.) — confirmed by Table 3.42 (FPC, PPC—Input and Holding—PMP2) and Table 30 (Liebert PowerSure Interactive) of SL-28170

generated by gemini:gemini-3.5-flash · harvested from https://www.ccontrols.com/support/dp/LiebertIntelliSlot.pdf (Vertiv); manual-faithful — the document's claims, panel risk: ELEVATED — panel is not confident; proved interop-verified on 2026-06-10 · recorded 2026-06-10

The trust ladder

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